In the past, synthesizers with phase lock loops (PLLs) which operate over a wide frequency range typically must adjust loop gain in order to maintain the desired bandwidth (BW). It has been well known that PLL BW=M×Kp×Kv/N where M is the integrator gain, Kp is phase detector gain, Kv is the voltage controlled oscillator (VCO) tune sensitivity, and N is the loop division ratio.
A prior art synthesizer is shown in FIG. 1. Typically, such synthesizers require that the VCO Kv be measured across the entire frequency band. Typically, this Kv measurement requires the synthesizer to be connected to external test equipment. From the Kv measurement, the optimum M or Kp can be determined to achieve the desired BW. Typically, the M or Kp is set either from an external control device or saved in a programmable memory within the synthesizer circuit. In such circuits, expensive VCOs with very tight Kv tolerances are used to minimize variability and shorten the test measurement time. If such synthesizers need repair, it is essential that a similar VCO with the same tight tolerances be used in the repaired device. If modifications are made to the circuit, it often is necessary to recalibrate (readjust M or Kp) the circuit. This requires time and expense.
Consequently, there exists a need for improved methods and systems for calibration of a synthesizer phase lock loop and automate the calibration process.